1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to techniques for controlling the formation of copper interconnects.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the size, or scale, of the components of a typical transistor also requires reducing the size and cross-sectional dimensions of electrical interconnects to contacts to active areas, such as N+(P+) source/drain regions and a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate conductor, and the like. As the size and cross-sectional dimensions of electrical interconnects get smaller, resistance increases and electromigration increases. Increased resistance and electromigration are undesirable for a number of reasons. For example, increased resistance may reduce device drive current, and source/drain current through the device, and may also adversely affect the overall speed and operation of the transistor. Additionally, electromigration effects in aluminum (Al) interconnects, where electrical currents actually carry aluminum (Al) atoms along with the current, causing them to electromigrate, may lead to degradation of the aluminum (Al) interconnects, further increased resistance, and even disconnection and/or delamination of the aluminum (Al) interconnects.
The ideal interconnect conductor for semiconductor circuitry will be inexpensive, easily patterned, have low resistivity, and high resistance to corrosion, electromigration, and stress migration. Aluminum (Al) is most often used for interconnects in contemporary semiconductor fabrication processes primarily because aluminum (Al) is inexpensive and easier to etch than, for example, copper (Cu). However, because aluminum (Al) has poor electromigration characteristics and high susceptibility to stress migration, it is typical to alloy aluminum (Al) with other metals.
As discussed above, as semiconductor device geometries shrink and clock speeds increase, it becomes increasingly desirable to reduce the resistance of the circuit metallization. The one criterion that is most seriously compromised by the use of aluminum (Al) for interconnects is that of conductivity. This is because the three metals with lower resistivities (aluminum, Al, has a resistivity of 2.824xc3x9710xe2x88x926 ohms-cm at 20xc2x0 C.), namely, silver (Ag) with a resistivity of 1.59xc3x9710xe2x88x926 ohms-cm (at 20xc2x0 C.), copper (Cu) with a resistivity of 1.73xc3x9710xe2x88x926 ohms-cm (at 20xc2x0 C.), and gold (Au) with a resistivity of 2.44xc3x9710xe2x88x926 ohms-cm (at 20xc2x0 C.), fall short in other significant criteria. Silver (Ag), for example, is relatively expensive and corrodes easily, and gold (Au) is very costly and difficult to etch. Copper (Cu), with a resistivity nearly on par with silver (Ag), a relatively high immunity to electromigration, high ductility and high melting point (1083xc2x0 C. for copper, Cu, vs. 660xc2x0 C. for aluminum, Al), fills it) most criteria admirably. However, copper (Cu) is difficult to etch in a semiconductor environment. As a result of the difficulty in etching copper (Cu), an alternative approach to forming vias and metal lines must be used. The damascene approach, consisting of etching openings such as trenches in the dielectric for lines and vias and creating in-laid metal patterns, is the leading contender for fabrication of sub-0.25 micron (sub-0.25xcexc) design rule copper-metallized (Cu-metallized) circuits.
In the damascene approach, a layer or film of copper is formed over the surface of the dielectric, filling the openings and/or trenches. The excess copper is then removed by polishing, grinding, and/or etching, such as by chemical/mechanical polishing, to leave only the copper in the openings or trenches, which form the copper interconnects. The surface of the copper interconnects, however, may remain rough or scratched by the removal process. This roughening of the surface of the copper interconnect may increase its resistance to the flow of current, reducing its effectiveness as a high-speed, low-resistance conductor.
Additionally, the surface of the copper interconnects may become contaminated by material removed from other portions of the wafer and/or elements found in the CMP slurry. These contaminants may likewise increase the resistance of the copper interconnect, reducing its effectiveness as a high-speed, low-resistance conductor. The contaminants may also have other undesirable effects on the copper interconnect and/or material deposited thereover, such as corrosion, surface flakes that can bridge Cu lines, surface defects and flakes that can result in future delamination of dielectric layers, surface defects that can increase resistance at an interface between a metal line and a metal via, or the like.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided. The method comprises forming a first dielectric layer above a first structure layer. Thereafter, a first opening is formed in the first dielectric layer, and a first copper layer is formed above the first dielectric layer and in the first opening. A portion of the first copper layer outside of the opening is removed. A surface portion of the first copper layer is also removed from within the opening, and a second layer of copper is formed above the first layer of copper, replacing the removed surface portion.
In another aspect of the present invention, a semiconductor device is provided. The semiconductor device is comprised of a first dielectric layer positioned above a first structure layer and having a first opening formed therein. A copper interconnect is deposited in the first opening. The copper interconnect has a first and second region wherein the second region forms an upper surface above the first region of the copper interconnect. The second region is formed by a selective deposition process.